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Automated Parasitic Extraction for IC Packages

Product Overview

TPA fully characterizes an entire package structure and automatically produces lumped or distributed RLC (Resistance, Inductance, and Capacitance) values for any lead or coupled groups of leads in matrix format or in SPICE sub-circuit format. These models can be generated directly from package layout tools coming from Synopsys, Cadence and Zuken, and exported into existing SPICE tools (SPICE/IBIS format) for subsequent timing analyses.

Working in Your Design Flow
TPA can be integrated directly into electronic package layout tools, such as Synopsys Encore™, Cadence Advanced Package Designer (APD), and Zuken CR-5000, to provide package engineers with a seamless design flow, automatically generating RLC models. The resulting electrical models can then be exported to and analyzed within Ansoft Designer®/DesignerSI™, Nexxim® or other SPICE-compatible circuit tools.